1. Field of the Invention
The invention relates to a semiconductor device containing a self-test circuit, and particularly to a semiconductor circuit for self-testing a tested circuit for a dynamic failure, for example, an out-of-tolerance propagation delay of the tested circuit.
2. Description of the Related Art
A built-in self-test ("BIST") method is a test technique in which a device for testing a part or all of a semiconductor integrated device is mounted upon the pertinent semiconductor integrated device. Details of the BIST method are disclosed in literature such as "Built-In Self-Test Techniques" and "Built-In Self-Test Structures" (IEEE Design & Test of Computers, Vol. 2, No. 2, April 1985, pp 21-36, Edward J. McCluskey). Also, a conventional semiconductor device provided with a self-test circuit, which is not directly relevant to the present invention, is disclosed in Japanese Patent Laid-Open Publication (Kokai) No. Heisei 1-277782. This publication discloses the elimination of the need for an output terminal for testing. This is done by judging the occurrence of a failure in a semiconductor device that is provided with a self-test circuit based on a change in a power source current due to an automatic short-circuit of the power source when the failure has occurred.
FIG. 5 shows the basic configuration of a conventional semiconductor device having a BIST device. In FIG. 5, the semiconductor device has a tested circuit 130 that is a part for performing the primary processing in the pertinent semiconductor device and subjected to the test by the BIST method and a group of circuits for testing.
A selector circuit 120 receives a test signal from an input signal generating circuit 110 and a normal signal from a normal input terminal "IN". The selector circuit 120 selectively provides an output to the tested circuit 130 in response to the logical values "1" and "0" of a signal "TEST" that is supplied to a test/normal mode switching signal terminal "TEST". A divider circuit 140 receives an output signal from the tested circuit 130, and selectively switches between the extraction of the test signal and the output of a normal signal from a normal output terminal "OUT," in response to logical values "1" and "0" of the signal "TEST," in the same way as the selector circuit 120. For example, when the normal signal is supplied from the selector circuit 120 to the tested circuit 130 in response to the logical value "0" of the signal "TEST", the divider circuit 140 outputs, from the normal output terminal "OUT," the output of the normal signal from the tested circuit 130. When the test signal is supplied from the selector circuit 120 to the tested circuit 130, the divider circuit 140 extracts the output of the test signal from the tested circuit 130.
The input signal generating circuit 110 generates a spatially and temporally predefined test signal in synchronization with a clock signal to be supplied to a synchronizing clock input signal terminal "CLOCK". Here, the meaning of spatially predefined is that the number of signals to be generated at the same time is defined. Also, the meaning of temporally defined is that the number of signals which can be generated in a specified time sequence is defined.
An output signal compression circuit 150 compresses a time series output signal resulting from the testing operation by the tested circuit 130 in synchronization with the clock signal to be supplied to the synchronizing clock input signal terminal "CLOCK".
An output signal expected value generating circuit 160 generates an expected value for the response output from the tested circuit 130, with respect to the test signal based upon the input signal generating circuit 110. However, the output signal expected value generating circuit 160 generates a compressed value of the pertinent expected value in accordance with the output from the output signal compression circuit 150. The compressed value output of the expected value is compared, by a comparator 170, with a compressed signal output as the test result from the output signal compression circuit 150. A judged result is then output through a judged value output signal terminal "JUDGE". By reading the judged result, it can be judged whether or not the tested circuit 130 is good.
FIG. 6 is a time chart showing wave forms of the conventional BIST device when in the test mode shown in FIG. 5. The following description of the operation of the conventional BIST device is made with reference to FIG. 6.
A synchronizing clock signal with a cycle "T" is applied to the synchronizing clock input signal terminal "CLOCK", and the wave forms shown in FIG. 6 are for about one cycle.
First, a test signal is generated by the input signal generating circuit 110 in response to the leading edge of a synchronizing clock signal. This test signal is supplied to a joint "a," namely the input terminal of the tested circuit 130, after a delay time {tla} through the selector circuit 120. This is because the output from the input signal generating circuit 110 is selected by the selector circuit 120 in the test mode.
Then, as the response by the tested circuit 130 to the test signal, a test result signal is output after a propagation delay {tab} from a joint "b", namely the output terminal from the tested circuit 130. The test result signal is further supplied to a joint "c", namely the input terminal of the output signal compression circuit 150, after a delay time {tbc} through the divider circuit 140.
Next, the test result signal is delayed for a setup time {tsetup}, and compressed by the output signal compression circuit 150 in response to the leading edge of the synchronizing clock signal of the next cycle. Then after a delay time {tsd}, the signal is output from a joint "d", namely the output of the output terminal signal compression circuit 150.
A sum of a duration of the above-described conventional BIST device, that begins with the leading edge of the synchronizing clock signal with the cycle "T" that is supplied to the synchronizing clock input signal terminal "CLOCK", continuing through the duration of the propagation of the test result signal to the input terminal of the output signal compression circuit 150, namely joint "c," and continuing until a setup time is reached, that shall be kept with respect to the leading edge of the synchronizing clock signal of the next cycle "T" to compress the pertinent test result signal by the output signal compression circuit 150, is represented by the following mathematical expression (hereinafter "expression") (1): EQU {tla}+{tab}+{tbc}+{tsetup} (1)
The propagation delay {tab} of the tested circuit 130 generally has a large value as compared with other propagation delays such as {tla}, {tbc} and the setup time {tsetup}. Assuming that the tested circuit 130 does not have any static failure such as an open failure or a short-circuit failure, if the cycle "T" of the synchronizing clock signal is given by the following expression (2), the test result is judged to be good, i.e., valid. However, if the cycle "T" of the synchronizing clock signal is given by the following expression (3), the test result is judged to be no good, i.e., it is considered to be not valid: EQU [T].gtoreq.[{tla}+{tab}+{tbc}+{tsetup}] (2) EQU [T]&lt;[{tla}+{tab}+{tbc}+{tsetup}] (3)
Therefore, the cycle "T" of the synchronizing clock signal is made variable to judge whether the test result is good or defective, so that a dynamic failure in the tested circuit 130 can be evaluated. The dynamic failure in the tested circuit 130 is, for example, an out-of-tolerance failure of a propagation delay.
But, the cycle "T" of the synchronizing clock signal is limited by the performance of the clock signal generating device that is provided outside of the semiconductor device. The cycle "T" is also limited by the performance of a main input buffer through which the semiconductor device first receives a signal from the outside. For example, the cycle of a signal which can be entered into a large-scale integrated logical circuit device of complementary field-effect transistors is in a general range of about ten nanoseconds. On the other hand, the propagation delay of the tested circuit 130 is generally fast as compared with the cycle of a signal which can be entered into the main input buffer. For example, the propagation delay for a random access memory mounted on a gate array, as the subject of the tested circuit, is about several nanoseconds.
Therefore, it is apparent that the conventional BIST device cannot evaluate the above-described dynamic failure.